Sample projects
⇒ Verification in C-based environment. FPGA prototype debug (wireless sensor network chip)
⇒ FFT/IFFT core and testbench development(eda company project to showcase tool)
⇒ Module and testbench development, integration.(configurable video-dsp chip)
⇒ Microarchitecture, rtl and testbench development, FPGA targeting(graphics chip)
⇒ 10 Gigabit Ethernet MAC development
⇒ Embedded Bluetooth transceiver development
⇒ Networking Switch ASICs verification
⇒ 3GPP base-station prototype development
⇒ Verification in C-based environment. FPGA prototype debug (wireless sensor network chip)
• Verilog model of a linear oscillator chip, for more accurate simulation of lab prototype
• Lab work – Chipscope
• Condensed, improved/refined, clarified, removed outdated information from client chip specification. Created fresh spec of register-space map.
• Began process of manufacturing test vector generation.
⇒ FFT/IFFT core and testbench development(eda company project to showcase tool)
• Fast 128-point FFT/IFFT soft core.
- Efficient architecture utilizing constant coefficient multiplications
- Four parallel datapaths
- Efficient architecture utilizing constant coefficient multiplications
• Developed spec and two rtl implementations exploring two architectures.
• Developed a simple Verilog testbench and a higher-level SystemC testbench.
• Implemented in TSMC 90nm library.
⇒ Module and testbench development, integration.(configurable video-dsp chip)
• Rtl module development (spec, implementation, verification) for multiple modules, including CCIR656 Decoder, DMA engine, and various minor
peripheral interfaces
• Integrated 3rd party IP and VIP and verified in SoC environment, including USB interface.
• Co-developed DSP software for configurable VLIW video decoder – Chinese AVS standard (similar to H.264 AVC). This work was performed for a
sister company of the hardware company (which had complementary technology).
⇒ Microarchitecture, rtl and testbench development, FPGA targeting (graphics chip)
• Developed rtl and testbench for floating-point math modules.
• Worked with chief architect to flesh out the micro-architecture of a few main modules. Wrote two major module micro-architecture specs.
• Developed rtl and testbench for the primary datapath module which contained complex mux/arbitration logic and all math computation modules.
Modified spec, rtl, and testbench in response to changing requirements.
• Inherited (and updated significantly) two submodule testbenches to encapsulate data structures in classes and made use of other
SystemVerilog abstractions to make the testbench more modular and readable.
• Used an early version of a new structured-asic flow for synthesis and place-and-route.
• Became initial driver for Altera FPGA build flow, developing auto-build scripts (for features like revision registers) and creating debug builds
with SignalTap.
⇒ 10 Gigabit Ethernet MAC development
CLIENT
A networking company developing next-generation connectivity products
CHALLENGE
To co-development a 10GbE MAC core. Core was used as a standalone chip as well as a reusable module.
SOLUTION
• Added two engineers to the client's two-person team
• Coded half of the RTL (~200K gates) including:
- input and output data interfaces
- input packet analysis for:
• address filtering
• length and CRC checking
- output framer and packet builder block for:
• header (address and length) generation
• CRC generation
- proprietary 200MHz 64bit host data interface
• Prototyped in a Xilinx Virtex FPGA
• Assisted with verification
• Performed top-level integration
• Operational line speed of 9.8Mbit/sec (OC192 SONET PHY level)
BENEFIT
The client successfully co-developed a next-generation MAC core which debuted as a stand-alone chip.
⇒ Embedded Bluetooth transceiver development
CLIENT
A mid-sized European OEM.
CHALLENGE
To develop a multi-purpose microcontroller chip with an integrated Bluetooth controller.
SOLUTION
• Developed a specification, incorporating a proprietary microcontroller design, Bluetooth version 1.2, and USB 1.1
• Formed a core team of 3 design and 3 verification engineers
• Developed the RTL code (approximately 1 million gates)
• Incorporated built-in self tests and a DFT strategy for interface checking
• Synthesized and performed P&R and floor-planning
• Performed verification using a custom-built testbench
• Prototyped device in a Xilinx Virtex-2E FPGA
• Tested on a custom PCB which the team created
• Chip incorporated USB and UART ports for accessing the internal RAM
• Fabricated ASIC in the 0.25um process
• Utilized Ambit, Silicon, Dracula, DRC & LVS, Calibre, and other EDA tools
BENEFIT
The device was successfully developed and is now being targeted to enter the marketplace.
⇒ Networking Switch ASICs verification
CLIENT
A multinational networking and telecommunications company with revenues of over one billion dollars
CHALLENGE
To verify three high-performance multi-protocol network processor designs at the RTL stage. The designs, of 2-3 million gates each, were:
a forwarding engine based on the OC48 standard, a general queue manager based on the OC48 standard, and a combined forwarding and
queuing engine based on the OC192 standard. Verification incorporated the following protocols: PCI/PCI-X, CSIX, FFE, SPI3, SPI4, UTOPIA-IV,
Ethernet, ATM, AAL5, and ATM over MPLS.
SOLUTION
• Formed an eight-person remote-site co-verification team
• Refined test strategy with client and developed test plan for the feature list
• Architected and created an object-oriented, script-based verification environment using Vera, Verilog, Perl, and makefiles. Environment
included data generators, protocol monitors, and performance and statistical analyzers
• Developed behavioral models of an OIF SPI4.2, a high speed ASIC-to-ASIC bus (UTOPIA-3 like), an Rx/Tx block and other devices. Worked
with PCI and PCI-X slave models
• Performed functional verification with directed and directed-random testcases using Vera, Verilog, 0-In, and SureFire
• Developed a tool and tests for performance measurement of the main datapath
• Assisted in debugging and rewrote some parts of the RTL code
• Performed coverage analysis and managed regression testing
BENEFIT
Over the course of this 30 month relationship, three complex multi-protocol routing switches were verified. These ASICs were fabricated and
successfully released in products. The client lowered its budget with an expandable staff which grew from four to eight and reached thirteen during
a peak period. More importantly, by utilizing the technical expertise of 74ze's engineers, their three ASICs were right the first time.
⇒ 3GPP base-station prototype development
CLIENT
A Canadian communications company
CHALLENGE
To develop and implement a MUD (multi-user detection) algorithm in a 3GPP (CDMA) base station system to provide communication, control,
and monitoring of mobile users, as well as communication with a PSTN. The implementation must be proven in a computer simulation model
and then in hardware. Objective was to spark investor interest. (1999)
SOLUTION
• Worked with customer to analyze their requirements and to set milestones
• Assembled staff of 10 engineers (a DSP software designer, FPGA designers, PCB designers, and C programmers)
• Solidified project communication channel by working at client-site temporarily and through client visits
• Created a software model and simulated
• Developed a hardware prototype using
• TI TMS320C62x DSP processors and Code Composer Studio
• Xilinx FPGAs and Alliance suite and Synplicity's Synplify
• ModelSim, Aldec, and Synopsys tools
• an RF unit for transmitting/receiving
• a PC to evaluate the performance characteristics using CVI Lab/C++
BENEFIT
A 3GPP Base Station Modem prototype was successfully created and demonstrated improved performance characteristics to investors
within one-year of the start date. The prototype implemented a unique MUD algorithm, which showed a significant decrease in the bit error rate
and an improvement in the signal-to-noise ratio.
