About Us

Digital Chip Engineer – Verification

Seeking an experienced verification engineer who has experience using a higher level of abstraction than vanilla Verilog for verification. Ideal candidate is a senior engineer who is capable of sticking to agreed upon tasks (not signing up for more than is do-able) and executing flawlessly.
Common tasks will include converting specs into behavioral models and improving legacy testbenches by incorporating verification abstractions to improve controllability and ease of test generation. On-site work will be required 40% - 100% of the time.

    • 5 or more years of experience
    • Clear test plan writing and requirements gathering experience
    • SystemVerilog (or SystemC)
    • C/C++
    • experience with OOP (object-oriented programming)
    • scripting

    • OVM/UVM verification methodology experience
    • previous contract experience
    • SystemVerilog assertion usage
    • WiFi protocol experience
    • Video processing experience

We are always interested in adding resumes to our database. Occasionally a short-notice need is fulfilled by an immediate search through our existing contacts.

Digital Chip Engineer – Verification

(same as above)
Russian-speaking and willing/able to travel between California and Moscow, Russia.

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